SN74LVC2G00W-EP - 增强型产品双路 2 输入正与非门

SN74LVC2G00W-EP是TI德州仪器公司的一款无产品，SN74LVC2G00W-EP是增强型产品双路 2 输入正与非门，本站介绍了SN74LVC2G00W-EP的封装应用图解、特点和优点、功能等，并给出了与SN74LVC2G00W-EP相关的TI元器件型号供参考。

SN74LVC2G00W-EP - 增强型产品双路 2 输入正与非门 - 无 - 小尺寸逻辑器件 - 德州仪器

产品描述

产品特性

Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Extended Temperature Performance of -55°C to 115°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree(1)
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5.3 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specifiedperformance and environmental limits.

DESCRIPTION/ORDERING INFORMATION

This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G00W-EP performs the Boolean function Y = A • B or Y = A + B in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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