ADC08500 - 高性能、低功耗 8 位、500 MSPS A/D 转换器

ADC08500是TI德州仪器公司的一款高速ADC(>10MSPS)产品，ADC08500是高性能、低功耗 8 位、500 MSPS A/D 转换器，本站介绍了ADC08500的封装应用图解、特点和优点、功能等，并给出了与ADC08500相关的TI元器件型号供参考。

ADC08500 - 高性能、低功耗 8 位、500 MSPS A/D 转换器 - 高速ADC(>10MSPS) - 模数转换器 - 德州仪器

产品描述

The ADC08500 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 0.8 Watts at 500 MSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

The converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

产品特性

Internal Sample-and-Hold
Single +1.9V ±0.1V Operation
Choice of SDR or DDR Output Clocking
Multiple ADC Synchronization Capability
Ensured No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and Offset
Duty Cycle Corrected Sample Clock

Key Specifications

Resolution 8 Bits
Max Conversion Rate 500 MSPS (min)
Bit Error Rate 10-18 (typ)
ENOB @ 250 MHz Input 7.5 Bits (typ)
DNL ±0.15 LSB (typ)
Power Consumption
- Operating 0.8 W (typ)
- Power Down Mode 3.5 mW (typ)

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