ADC10040-Q1 - 10 位、40 MSPS、3V、55.5 mW A/D 转换器

ADC10040-Q1是TI德州仪器公司的一款高速ADC(>10MSPS)产品，ADC10040-Q1是10 位、40 MSPS、3V、55.5 mW A/D 转换器，本站介绍了ADC10040-Q1的封装应用图解、特点和优点、功能等，并给出了与ADC10040-Q1相关的TI元器件型号供参考。

ADC10040-Q1 - 10 位、40 MSPS、3V、55.5 mW A/D 转换器 - 高速ADC(>10MSPS) - 模数转换器 - 德州仪器

产品描述

The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 55.5 mW at 40 MSPS, including the reference current. The Standby feature reduces power consumption to just 13.5 mW.

The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement.

The ADC10040Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 3 Qualified.

This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C.

产品特性

Single +3.0V Operation
Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing
400 MHz −3 dB Input Bandwidth
Low Power Consumption
Standby Mode
On-Chip Reference and Sample-and-Hold Amplifier
Offset Binary or Two’s Complement Data Format
Separate Adjustable Output Driver Supply to Accommodate 2.5V and 3.3V Logic Families
AEC-Q100 Grade 3 Qualified
28-Pin TSSOP Package

Key Specifications

Resolution: 10 Bits
Conversion Rate: 40 MSPS
Full Power Bandwidth: 400 MHz
DNL: ±0.3 LSB typ)
SNR (fIN = 11 MHz): 59.6 dB (typ)
SFDR (fIN = 11 MHz): -80 dB (typ)
Power Consumption, 40 MHz: 55.5 mW

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