ADC10D1000 - 低功耗、10 位、双路 1.0 GSPS 或单路 2.0 GSPS ADC

ADC10D1000是TI德州仪器公司的一款高速模数转换器(>=1GSPS)产品，ADC10D1000是低功耗、10 位、双路 1.0 GSPS 或单路 2.0 GSPS ADC，本站介绍了ADC10D1000的封装应用图解、特点和优点、功能等，并给出了与ADC10D1000相关的TI元器件型号供参考。

ADC10D1000 - 低功耗、10 位、双路 1.0 GSPS 或单路 2.0 GSPS ADC - 高速模数转换器(>=1GSPS) - 模数转换器 - 德州仪器

产品描述

The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.

产品特性

Excellent Accuracy and Dynamic Performance
Pin Compatible with ADC12D1000/1600/1800
Low Power Consumption, Further Reduced at Lower Fs
Internally Terminated, Buffered, Differential Analog Inputs
R/W SPI Interface for Extended Control Mode
Dual-Edge Sampling Mode, in Which the I- and Q-channels Sample One Input at Twice the Sampling Clock Rate
Test Patterns at Output for System Debug
Programmable 15-bit Gain and 12-bit Plus Sign Offset
Programmable tAD Adjust Feature
1:1 Non-demuxed or 1:2 Demuxed LVDS Outputs
AutoSync Feature for Multi-Chip Systems
Single 1.9V ± 0.1V Power Supply
292-Ball BGA Package (27mm x 27mm x 2.4mm with 1.27mm Ball-Pitch); No Heat Sink Required

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