ADC14155QML-SP - 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter

ADC14155QML-SP是TI德州仪器公司的一款高速ADC(>10MSPS)产品，ADC14155QML-SP是14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter，本站介绍了ADC14155QML-SP的封装应用图解、特点和优点、功能等，并给出了与ADC14155QML-SP相关的TI元器件型号供参考。

ADC14155QML-SP - 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter - 高速ADC(>10MSPS) - 模数转换器 - 德州仪器

产品描述

The ADC14155 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual +3.3V and +1.8V power supplies and consumes 967 mW of power at 155 MSPS.

The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation.

The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14155 can be operated with an external reference.

The Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC14155 is available in a 48-lead thermally ehanced mult-layer ceramic quad package and operates over the military temperature range of -55°C to +125°C.

产品特性

Total Ionizing Dose 100 krad(Si)
Single Event Latch-up 120 MeV-cm2/mg
1.1 GHz Full Power Bandwidth
Internal Sample-and-hold Circuit
Low Power Consumption
Internal Precision 1.0V Reference
Single-ended or Differential Clock Modes
Data Ready Output Clock
Clock Duty Cycle Stabilizer
Dual +3.3V and +1.8V Supply Operation (+/- 10%)
Power-down Mode
Offset Binary or 2's Complement Output Data Format
48-pin CFP Package, (11.5mm x 11.5mm, 0.635mm pin-pitch)

Key Specifications

Resolution 14 Bits
Conversion Rate 155 MSPS
SNR (fIN = 70 MHz) 70.1 dBFS (typ)
SFDR (fIN = 70 MHz) 82.3 dBFS (typ)
ENOB (fIN = 70 MHz) 11.3 bits (typ)
Full Power Bandwidth 1.1 GHz (typ)
Power Consumption 967 mW (typ)

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