ADC16DX370 - 双路 16 位 370 MSPS ADC， 7.4 Gbps JESD204B 输出

ADC16DX370是TI德州仪器公司的一款高速ADC(>10MSPS)产品，ADC16DX370是双路 16 位 370 MSPS ADC， 7.4 Gbps JESD204B 输出，本站介绍了ADC16DX370的封装应用图解、特点和优点、功能等，并给出了与ADC16DX370相关的TI元器件型号供参考。

ADC16DX370 - 双路 16 位 370 MSPS ADC， 7.4 Gbps JESD204B 输出 - 高速ADC(>10MSPS) - 模数转换器 - 德州仪器

产品特性

Resolution: 16-Bit
Conversion Rate: 370 MSPS
1.7 VP-P Input Full Scale Range
Performance:
- Input: 150 MHz, –3 dBFS
  - SNR: 69.6 dBFS
  - Noise Spectral Density: –152.3 dBFS/Hz
  - SFDR: 88 dBFS
  - Non-HD2 and Non-HD3 SPUR: –90 dBFS
Power Dissipation: 800 mW/channel
Buffered Analog Inputs
On-Chip Precision Reference Without External Bypassing
Input Sampling Clock Divider With Phase Synchronization (Divide-by- 1, 2, 4, or 8)
JESD204B Subclass 1 Serial Data Interface
- Lane Rates up to 7.4 Gb/s
- Configurable as 1- or 2-Lanes/Channel
Fast Over-Range Signals
4-Wire, 1.2-V, 1.8-V, 2.5-V, or 3-V Compatible Serial Peripheral Interface (SPI)
56-Pin WQFN Package, (8 × 8 mm, 0.5-mm Pin-Pitch)

产品应用

High IF Sampling Receivers
Multi-Carrier Base Station Receivers
- GSM/EDGE, CDMA2000, UMTS, LTE, WiMax
Diversity, Multi-Mode, and Multiband Receivers
Digital Pre-Distortion
Test and Measurement Equipment
Communications Instrumentation
Portable Instrumentation

产品说明

The ADC16DX370 device is a monolithic dual-channel high performance analog-to-digital converter capable of converting analog input signals into 16-bit digital words with a sampling rate of 370 MSPS. This converter uses a differential pipelined architecture with integrated input buffer to provide excellent dynamic performance while maintaining low power consumption.

The integrated input buffer eliminates charge kickback noise coming from the internal switched capacitor sampling circuits and eases the system-level design of the driving amplifier, anti-aliasing filter, and impedance matching. An input sampling clock divider provides integer divide ratios with configurable phase selection to simplify system clocking. An integrated low-noise voltage reference eases board level design without requiring external decoupling capacitors. The output digital data is provided through a JESD204B subclass 1 interface from a 56-pin, 8-mm × 8-mm WQFN package. A SPI is available to configure the device that is compatible with 1.2-V to 3-V logic.

产品器件信息

PART NUMBER	PACKAGE	BODY SIZE (NOM)
ADC16DX370	WQFN (56)	8.00 × 8.00 mm

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