• Dual-Channel ADCs
• 14-Bit Resolution
• Maximum Clock Rate: 160 MSPS
• JESD204B Serial Interface
  • Subclass 0, 1, 2 Compliant
  • Up to 3.125 Gbps
  • Two- and Four-Lane Support
• Analog Input Buffer with High-Impedance Input
• Flexible Input Clock Buffer: Divide-by-1, -2, and -4
• Differential Full-Scale Input: 2 VPP and 2.5 VPP (Register Programmable)
• Package: 9-mm × 9-mm QFN-64
• Power Dissipation: 679 mW/Ch
• Aperture Jitter: 85 fS rms
• Internal Dither
• Channel Isolation: 100 dB
• Performance:
  • fIN = 170 MHz at 2 VPP, –1 dBFS
    • SNR: 72.9 dBFS
    • SFDR: 90 dBc for HD2, HD3
    • SFDR: 100 dBc for Non HD2, HD3
  • fIN = 170 MHz at 2.5 VPP, –1 dBFS
    • SNR: 74.2 dBFS
    • SFDR: 84 dBc for HD2, HD3 and 95 dBc for Non HD2, HD3

• Communication and Cable Infrastructure
• Multi-Carrier, Multimode Cellular Receivers
• Radar and Smart Antenna Arrays
• Broadband Wireless
• Test and Measurement Systems
• Software-Defined and Diversity Radios
• Microwave and Dual-Channel I/Q Receivers
• Repeaters
• Power Amplifier Linearization

The ADS42JB46 is a high-linearity, dual-channel, 14-bit, 160-MSPS, analog-to-digital converter (ADC). This device supports the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy, thus making driving analog inputs up to very high input frequencies easy. A sampling clock divider allows more flexibility for system clock architecture design. The device employs internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.