ADS54J40 - ADS54J40 双通道 14 位 1.0GSPS 数模转换器

ADS54J40是TI德州仪器公司的一款高速模数转换器(>=1GSPS)产品，ADS54J40是ADS54J40 双通道 14 位 1.0GSPS 数模转换器，本站介绍了ADS54J40的封装应用图解、特点和优点、功能等，并给出了与ADS54J40相关的TI元器件型号供参考。

ADS54J40 - ADS54J40 双通道 14 位 1.0GSPS 数模转换器 - 高速模数转换器(>=1GSPS) - 模数转换器 - 德州仪器

产品特性

14-Bit Resolution, Dual-Chanel, 1-GSPS ADC
Noise Floor: –158 dBFS/Hz
Spectral Performance (fIN = 170 MHz at –1 dBFS):
- SNR: 69.0 dBFS
- NSD: –155.9 dBFS/Hz
- SFDR: 86 dBc
- SFDR: 89 dBc (Except HD2, HD3, and Interleaving Tones)
Spectral Performance (fIN = 350 MHz at –1 dBFS):
- SNR: 66.3 dBFS
- NSD: –153.3 dBFS/Hz
- SFDR: 75 dBc
- SFDR: 85 dBc (Except HD2, HD3, and Interleaving Tones)
Channel Isolation: 100 dBc at fIN = 170 MHz
Input Full-Scale: 1.9 VPP
Input Bandwidth (3 dB): 1.2 GHz
On-Chip Dither
Integrated Wideband DDC Block
JESD204B Interface with Subclass 1 Support:
- 2 Lanes per ADC at 10.0 Gbps
- 4 Lanes per ADC at 5.0 Gbps
- Support for Multi-Chip Synchronization
Power Dissipation: 1.35 W/ch at 1 GSPS
VQFNP-72 Package (10 mm × 10 mm)

产品应用

Radar and Antenna Arrays
Broadband Wireless
Cable CMTS, DOCSIS 3.1 Receivers
Communications Test Equipment
Microwave Receivers
Software Defined Radio (SDR)
Digitizers

产品说明

The ADS54J40 is a low-power, wide-bandwidth, 14-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –158dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J40 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

Device Information

PART NUMBER	SPEED GRADE (MSPS)	RESOLUTION (Bits)
ADS54J40	1000	14
ADS54J60	1000	16

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