ADS54J69 - ADS54J69 数据表

ADS54J69是TI德州仪器公司的一款高速ADC(>10MSPS)产品，ADS54J69是ADS54J69 数据表，本站介绍了ADS54J69的封装应用图解、特点和优点、功能等，并给出了与ADS54J69相关的TI元器件型号供参考。

ADS54J69 - ADS54J69 数据表 - 高速ADC(>10MSPS) - 模数转换器 - 德州仪器

产品特性

16-Bit Resolution, Dual-Channel, 500-MSPS ADC
Noise Floor: –159 dBFS/Hz
Spectral Performance (fIN = 170 MHz at –1 dBFS):
- SNR: 73 dBFS
- NSD: –157 dBFS/Hz
- SFDR: 91 dBc
- SFDR: 97 dBc (Except HD2, HD3, and Interleaving Tone)
Spectral Performance (fIN = 350 MHz at –1 dBFS):
- SNR: 69.5 dBFS
- NSD: –153.5 dBFS/Hz
- SFDR: 75 dBc
- SFDR: 88 dBc (Except HD2, HD3, and Interleaving Tone)
Channel Isolation: 100 dBc at fIN = 170 MHz
Input Full-Scale: 1.9 VPP
Input Bandwidth (3 dB): 1.2 GHz
On-Chip Dither
Integrated Decimate-by-2 Filter
JESD204B Interface with Subclass 1 Support:
- 1 Lane per ADC at 10.0 Gbps
- 2 Lanes per ADC at 5.0 Gbps
- Support for Multi-Chip Synchronization
Power Dissipation: 1.35 W/ch at 500 MSPS
VQFNP-72 Package (10 mm × 10 mm)

产品应用

Radar and Antenna Arrays
Broadband Wireless
Cable Infrastructure
Communications Test Equipment
Microwave Receivers

产品说明

The ADS54J69 is a low-power, wide-bandwidth, 16-bit, 500-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting one or two lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel is directly connected to a wideband digital down-converter (DDC) block. The ADS54J69 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.

Device Information

PART NUMBER	SPEED GRADE (MSPS)	RESOLUTION (Bits)
ADS54J40	1000	14
ADS54J60	1000	16
ADS54J69	500	16

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