ADS58C48 - 具有 SNRBoost 的四路 11 位 200MSPS ADC

ADS58C48是TI德州仪器公司的一款高速ADC(>10MSPS)产品，ADS58C48是具有 SNRBoost 的四路 11 位 200MSPS ADC，本站介绍了ADS58C48的封装应用图解、特点和优点、功能等，并给出了与ADS58C48相关的TI元器件型号供参考。

ADS58C48 - 具有 SNRBoost 的四路 11 位 200MSPS ADC - 高速ADC(>10MSPS) - 模数转换器 - 德州仪器

产品描述

The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications.

The ADS58C48 uses third-generation SNRBoost3G technology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in the SNRBoost3G technology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separate SNRBoost3G coefficients can be programmed for each channel.

The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset.

The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of the LVDS output buffers can be increased to support 50 ohms differential termination. This allows the output clock signal to be connected to two separate receiver chips with an effective 50 termination (such as the two clock ports of the GC5330).

The same digital output pins can also be configured as a parallel 1.8V CMOS interface.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C).

产品特性

Maximum Sample Rate: 200 MSPS
High Dynamic Performance
- SFDR 82 dBc at 140 MHz
- 72.3 dBFS SNR in 60 MHz BW Using SNRBoost3G technology
SNRBoost3G Highlights
- Supports Wide Bandwidth up to 60 MHz
- Programmable Bandwidths – 60 MHz, 40 MHz, 30 MHz, 20 MHz
- Flat Noise Floor within the Band
- Independent SNRBoost3G Coefficients for Every Channel
Output Interface
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
  - Standard Swing: 350mV
  - Low Swing: 200mV
  - Default Strength: 100 Termination
  - 2x Strength: 50 Termination
- 1.8V Parallel CMOS Interface Also Supported
Ultra-Low Power with Single 1.8V Supply
- 0.9W Total Power
- 1.32 W Total Power (200 MSPS) with SNRBoost3G on all 4 Channels
- 1.12 W Total Power (200 MSPS) with SNRBoost3G on 2 Channels
Programmable Gain up to 6dB for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude
80-TQFP Package

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