ADS62C15 - 具有 SNRBoost 的双通道 11 位 125MSPS ADC

ADS62C15是TI德州仪器公司的一款高速ADC(>10MSPS)产品，ADS62C15是具有 SNRBoost 的双通道 11 位 125MSPS ADC，本站介绍了ADS62C15的封装应用图解、特点和优点、功能等，并给出了与ADS62C15相关的TI元器件型号供参考。

ADS62C15 - 具有 SNRBoost 的双通道 11 位 125MSPS ADC - 高速ADC(>10MSPS) - 模数转换器 - 德州仪器

产品描述

ADS62C15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62C15 uses proprietary technology that can be used to overcome SNR limitation due to quantization noise (for bandwidths less than Nyquist, Fs/2). It includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. The device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

产品特性

Maximum Sample Rate: 125 MSPS
11-Bit Resolution With No Missing Codes
82 dBc SFDR at Fin = 117 MHz
67 dBFS SNR at Fin = 117 MHz
77.5 dBFS SNR at Fin = 117 MHz, 20MHz bandwidth using technology
92 dB Crosstalk
Parallel CMOS and DDR LVDS Output Options
3.5 dB Coarse Gain and Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off
Digital Processing Block With:
- Offset Correction
- Fine Gain Correction, in Steps of 0.05 dB
- Decimation by 2/4/8
- Built-in and Custom Programmable 24-Tap Low/High/ Band Pass Filters
Supports Sine, LVPECL, LVDS and LVCMOS Clocks and Amplitude Down to 400 mVPP
Clock Duty Cycle Stabilizer
Internal Reference; Also Supports External Reference
64-QFN Package (9mm × 9mm)

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