ADS6425 - Low power monolithic 4-channel, 12-bit 125MSPS ADC

ADS6425是TI德州仪器公司的一款高速ADC(>10MSPS)产品，ADS6425是Low power monolithic 4-channel, 12-bit 125MSPS ADC，本站介绍了ADS6425的封装应用图解、特点和优点、功能等，并给出了与ADS6425相关的TI元器件型号供参考。

ADS6425 - Low power monolithic 4-channel, 12-bit 125MSPS ADC - 高速ADC(>10MSPS) - 模数转换器 - 德州仪器

产品描述

The ADS6425 is a high performance 12-bit, 125-MSPS quad channel ADC. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes a 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC's data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS6425 also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes, and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

The ADS6425 has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (-40°C to 85°C).

产品特性

Maximum Sample Rate: 125 MSPS
12-Bit Resolution with No Missing Codes
1.65-W Total Power
Simultaneous Sample and Hold
70.3 dBFS SNR at Fin = 50 MHz
83 dBc SFDR at Fin = 50 MHz, 0 dB Gain
79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain
3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SFDR/SNR Trade-Off
Serialized LVDS Outputs with Programmable Internal Termination Option
Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVpp Differential
Internal Reference with External Reference Support
No External Decoupling Required for References
3.3-V Analog and Digital Supply
64 QFN Package (9 mm × 9 mm)
Pin Compatible 14-Bit Family (ADS644X - SLAS532)
APPLICATIONS
- Base-Station IF Receivers
- Diversity Receivers
- Medical Imaging
- Test Equipment

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