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CD4043B-MIL - 产品图解：
CD4043B-MIL-具有三态输出的 CMOS 四路或非 R/S 锁存器
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TI产品 - CD4043B-MIL介绍

CD4043B-MIL - 具有三态输出的 CMOS 四路或非 R/S 锁存器

CD4043B-MIL是TI德州仪器公司的一款其它锁存器产品，CD4043B-MIL是具有三态输出的 CMOS 四路或非 R/S 锁存器，本站介绍了CD4043B-MIL的封装应用图解、特点和优点、功能等，并给出了与CD4043B-MIL相关的TI元器件型号供参考。

CD4043B-MIL - 具有三态输出的 CMOS 四路或非 R/S 锁存器 - 其它锁存器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

产品特性

  • 3-state outputs with common output ENABLE
  • Separate SET and RESET inputs for each latch
  • NOR and NAND configurations
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications
    • Holding register in multi-register system
    • Four bits of independent storage with output ENABLE
    • Strobed register
    • General digital logic
    • CD4043B for positive logic systems
    • CD4044B for negative logic systems

Data sheet acquired from Harris Semiconductor

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