

- DS16EV5110SQX/NOPB - 集成电路(IC) > 接口 > 专用
- SN74F174ANSRG4 - 逻辑 - 触发器
- CD4073BEE4 - 集成电路(IC) > 逻辑 > 门和反相器
- MSP430F6633IZQWR - 集成电路(IC) > 嵌入式 > 微控制器
- LM3S5P31-IBZ80-C5T - 嵌入式 - 微控制器
- SN10KHT5541DWR - 集成电路(IC) > 逻辑 > 转换器,电平移位器
- TMS320TCI6487FGUNA - 集成电路(IC) > 嵌入式 > DSP(数字信号处理器)
- ADS131M04IPWT - 集成电路(IC) > 数据采集 > 模数转换器(ADC)
- TPS54283PWPR - 集成电路(IC) > 电源管理(PMIC) > 稳压器 - DC-DC 开关稳压器
- UCC2813QDR-0Q1 - 集成电路(IC) > 电源管理(PMIC) > DC-DC 开关控制器
- TRSF3222EIDBG4 - 集成电路(IC) > 接口 > 驱动器,接收器,收发器
- SN65LVDS315RGER - 集成电路(IC) > 接口 > 串行器,解串器
- TPS79942DDCRG4 - 集成电路(IC) > 电源管理(PMIC) > 稳压器 - 线性
- LMX2336USLBX - 集成电路(IC) > 时钟/定时 > 时钟发生器,PLL,频率合成器
- SN74LVC257ADB - 集成电路(IC) > 逻辑 > 信号开关,多路复用器,解码器
- TLC69668QRTWRQ1 - 集成电路(IC) > 电源管理(PMIC) > LED 驱动器
- TPS61166DSKT - 集成电路(IC) > 电源管理(PMIC) > LED 驱动器
- SN74LVC863ADWRG4 - 逻辑 - 缓冲器,驱动器,接收器,收发器
- LM5150QRUMRQ1 - 集成电路(IC) > 电源管理(PMIC) > DC-DC 开关控制器
- TPA3122D2N - 集成电路(IC) > 线性 > 放大器 > 音频放大器



CDC509 - 3.3V 锁相环时钟驱动器
CDC509是TI德州仪器公司的一款无产品,CDC509是3.3V 锁相环时钟驱动器,本站介绍了CDC509的封装应用图解、特点和优点、功能等,并给出了与CDC509相关的TI元器件型号供参考。
CDC509 - 3.3V 锁相环时钟驱动器 - 无 - 零延迟缓冲器 - 德州仪器
The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCC and is designed to drive up to five clock loads per output.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDC509 is characterized for operation from 0°C to 70°C.
- Use CDCVF2509A as a Replacement for this Device
- Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
- Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
- Separate Output Enable for Each Output Bank
- External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input
- No External RC Network Required
- Operates at 3.3-V VCC
- Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package
- TS3DV520 - 用于 DVI/DMI 应用领域的 5 通道差动 10:20 MUX 开关
- LDC1314 - 具有 I2C 的四通道、12 位电感数字转换器
- DS90CP02 - 1.5 Gbps 2x2 LVDS 交叉点交换器
- TPS53126 - 双路同步 用于低压电源轨的降压控制器,频率为 350kHz 或 700kHz
- TMS570LC4357 - TMS570LC4357 16 位和 32 位 RISC 闪存微控制器(INT,PP)
- SN74V3680 - 16384 x 36 同步 FIFO 存储器
- SN74LVC02A - 四路 2 输入正或非门
- TMS320C6452 - 数字信号处理器
- SM320DM355-EP - 数字媒体片上系统 (DMSoC)
- CDCEL925 - 具有 1.8V LVCMOS 输出的可编程 3-PLL VCXO 时钟合成器



