

- UCC2917N - 集成电路(IC) > 电源管理(PMIC) > 热插拔控制器
- SN75LVDT388ADBTG4 - 集成电路(IC) > 接口 > 驱动器,接收器,收发器
- LM4040DIZ-5.0 - 集成电路(IC) > 电源管理(PMIC) > 电压基准
- LM4050AEM3X-2.5 - 集成电路(IC) > 电源管理(PMIC) > 电压基准
- PT4852A - 直流转换器
- MAX4595DBVR - 集成电路(IC) > 接口 > 模拟开关,多路复用器,解复用器
- AFE4404YZPT - 集成电路(IC) > 数据采集 > 模拟前端(AFE)
- TPS65930BZCH - 集成电路(IC) > 电源管理(PMIC) > 电源管理 - 专用
- CY74FCT257CTDG4 - 逻辑 - 信号开关,多路复用器,解码器
- LM2937ES-8.0 - 集成电路(IC) > 电源管理(PMIC) > 稳压器 - 线性
- TLV320AIC1110EVM - 开发板,套件,编程器 > 评估板 > 评估和演示板及套件
- LM2931CT/NOPB - 集成电路(IC) > 电源管理(PMIC) > 稳压器 - 线性
- LP38693MPX-ADJ - 集成电路(IC) > 电源管理(PMIC) > 稳压器 - 线性
- SN74HC273NSR - 集成电路(IC) > 逻辑 > 触发器
- V62/23618-01XE - 集成电路(IC) > 逻辑 > 缓冲器,驱动器,接收器,收发器
- TLC555CPWR - 集成电路(IC) > 时钟/定时 > 可编程定时器和振荡器
- JM54AC244S2A-RH - 集成电路(IC) > 逻辑 > 缓冲器,驱动器,接收器,收发器
- LP5910-1.1BYKAR - 集成电路(IC) > 电源管理(PMIC) > 稳压器 - 线性
- TPS76918EVM-127 - 开发板,套件,编程器 > 评估板 > 线性稳压器评估板
- MSP430FR5992IRGZR - 集成电路(IC) > 嵌入式 > 微控制器



CDC509 - 3.3V 锁相环时钟驱动器
CDC509是TI德州仪器公司的一款无产品,CDC509是3.3V 锁相环时钟驱动器,本站介绍了CDC509的封装应用图解、特点和优点、功能等,并给出了与CDC509相关的TI元器件型号供参考。
CDC509 - 3.3V 锁相环时钟驱动器 - 无 - 零延迟缓冲器 - 德州仪器
The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCC and is designed to drive up to five clock loads per output.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDC509 is characterized for operation from 0°C to 70°C.
- Use CDCVF2509A as a Replacement for this Device
- Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
- Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
- Separate Output Enable for Each Output Bank
- External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input
- No External RC Network Required
- Operates at 3.3-V VCC
- Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package
- LM337L - 3 端子可调节稳压器
- TMS320F28068M - 具有 InstaSPIN-MOTION 的 Piccolo 微控制器
- SN75LVDS051 - 高速差动线路驱动器和接收器
- MSP430F5631 - MSP430F563x 混合信号微处理器
- SN54LVC00A - 四路 2 输入正与非门
- LM78S40 - 通用开关稳压器子系统
- AFE4400 - 用于心率监视器和低成本脉动式血氧计的集成模拟前端
- SN74HCT139 - 双路 2 线路至 4 线路解码器/多路解复用器
- ADS8864 - 具有 18 位、333kSPS 和串行接口的微功耗小型差动输入
- SN54HC08-DIE - Quadruple 2-Input Positive-AND Gates, SN54HC08-DIE



