CDCF5801A - 具有延迟控制和相位校正的时钟乘法器

CDCF5801A是TI德州仪器公司的一款通用产品，CDCF5801A是具有延迟控制和相位校正的时钟乘法器，本站介绍了CDCF5801A的封装应用图解、特点和优点、功能等，并给出了与CDCF5801A相关的TI元器件型号供参考。

CDCF5801A - 具有延迟控制和相位校正的时钟乘法器 - 通用 - 时钟发生器 - 德州仪器

产品描述

The CDCF5801A provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin, while strapping the LEADLAG pin to dc high or low. Further possible applications are:

Aligning the rising edge of the output clock signal to the input clock rising edge Avoiding PLL instability in applications that require very long PLL feedback lines Isolation of jitter and digital switching noise Limitation of jitter in systems with good ppm frequency stability

The CDCF5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions.

The CDCF5801A provides clock multiplication and division from a reference clock (REFCLK) signal. The device is optimized to have extremely low jitter impact from input to output. The predivider pins MULT[0:1] and post-divider pins P[0:2] provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 25 MHz to 280 MHz with clock input references (REFCLK) ranging from 12.5 MHz to 240 MHz. See for detailed frequency support. The selection of pins MULT[0:1] and P[1:2] determines the multiplication value of 1, 2, 4, or 8. The CDCF5801A offers several power-down/ high-impedance modes, selectable by pins P0, STOPB and PWRDN. Another unique capability of the CDCF5801A is the high sensitivity and wide common-mode range of the clock-input pin REFCLK by varying the voltage on the VDDREF pin. The clock signal outputs CLKOUT and CLKOUTB can be used independently to generate single-ended clock signals. The CLKOUT/CLKOUTB outputs can also be combined to generate a differential output signal suitable for LVDS, LVPECL, or HSTL/SSTL signaling. The CDCF5801A is characterized for operation over free-air temperatures of -40°C to 85°C.

产品特性

Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8
Fail-Safe Power Up Initialization
Programmable Bidirectional Delay Steps of 1.3 mUI
Output Frequency Range of 25 MHz to 280 MHz
Input Frequency Range of 12.5 MHz to 240 MHz
Low Jitter Generation
Single-Ended REFCLK Input With Adjustable Trigger Level (Works With LVTTL, HSTL, and LVPECL)
Differential/Single-Ended Output
Output Can Drive LVPECL, LVDS, and LVTTL
Three Power Operating Modes to Minimize Power
Low Power Consumption (< 190 mW at 280 MHz/3.3 V)
Packaged in a Shrink Small-Outline Package (DBQ)
No External Components Required for PLL
Spread Spectrum Clock Tracking Ability to Reduce EMI (SSC)
APPLICATIONS
- Video Graphics
- Gaming Products
- Datacom
- Telecom
- Noise Cancellation Created by FPGAs

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