CDCLVD1204 - 低抖动 2 路输入可选 1:4 通用 LVDS 缓冲器

CDCLVD1204是TI德州仪器公司的一款差动产品，CDCLVD1204是低抖动 2 路输入可选 1:4 通用 LVDS 缓冲器，本站介绍了CDCLVD1204的封装应用图解、特点和优点、功能等，并给出了与CDCLVD1204相关的TI元器件型号供参考。

CDCLVD1204 - 低抖动 2 路输入可选 1:4 通用 LVDS 缓冲器 - 差动 - 时钟缓冲器 - 德州仪器

产品描述

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs, (IN0, IN1), to 4 pairs of differential LVDS clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50 transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small 16-pin, 3-mm × 3-mm QFN package.

产品特性

2:4 Differential Buffer
Low Additive Jitter: <300 fs RMS in 10-kHz to 20-MHz
Low Output Skew of 20 ps (Max)
Universal Inputs Accept LVDS, LVPECL, and LVCMOS
Selectable Clock Inputs through Control Pin
4 LVDS Outputs, ANSI EAI/TIA-644A Standard Compatible
Clock Frequency up to 800 MHz
2.375 V–2.625 V Device Power Supply
LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
Packaged in 3 mm × 3 mm 16-Pin QFN (RGT)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

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