CDCLVD1212 - 低抖动 2 路输入可选 1:12 通用 LVDS 缓冲器

CDCLVD1212是TI德州仪器公司的一款差动产品，CDCLVD1212是低抖动 2 路输入可选 1:12 通用 LVDS 缓冲器，本站介绍了CDCLVD1212的封装应用图解、特点和优点、功能等，并给出了与CDCLVD1212相关的TI元器件型号供参考。

CDCLVD1212 - 低抖动 2 路输入可选 1:12 通用 LVDS 缓冲器 - 差动 - 时钟缓冲器 - 德州仪器

产品描述

The CDCLVD1212 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVDS clock outputs (OUT0, OUT11) with minimum skew for clock distribution. The CDCLVD1212 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1212 is specifically designed for driving 50 Ω transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open it disables the outputs (static). The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5 V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1212 is packaged in small 40-pin, 6mm × 6mm QFN package.

产品特性

2:12 Differential Buffer
Low Additive Jitter: <300 fs RMS in 10 kHz to 20 MHz
Low Output Skew of 50 ps (Max)
Universal Inputs Accept LVDS, LVPECL, LVCMOS
Selectable Clock Inputs Through Control Pin
12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
Clock Frequency up to 800 MHz
2.375–2.625 V Device Power Supply
LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
Industrial Temperature Range –40°C to 85°C
Packaged in 6mm × 6mm 40-Pin QFN (RHA)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

下面可能是您感兴趣的TI德州仪器公司差动元器件

TI公司产品现货专家，订购TI公司产品不限最低起订量，TI芯片大陆现货即时发货，香港库存3-5天发货，海外库存7-10天发货

寻找全球TI代理商现货货源 - TI公司（德州仪器）电子元件在线订购