CDCLVP1212 - 低抖动 2 路输入可选 1:12 通用 LVPECL 缓冲器

CDCLVP1212是TI德州仪器公司的一款差动产品，CDCLVP1212是低抖动 2 路输入可选 1:12 通用 LVPECL 缓冲器，本站介绍了CDCLVP1212的封装应用图解、特点和优点、功能等，并给出了与CDCLVP1212相关的TI元器件型号供参考。

CDCLVP1212 - 低抖动 2 路输入可选 1:12 通用 LVPECL 缓冲器 - 差动 - 时钟缓冲器 - 德州仪器

产品特性

2:12 Differential Buffer
Selectable Clock Inputs Through Control Terminal
Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL
12 LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 88 mA
Very Low Additive Jitter: <100 fs, rms in 10-kHz to 20-MHz Offset Range:
- 57 fs, rms (typ) @ 122.88 MHz
- 48 fs, rms (typ) @ 156.25 MHz
- 30 fs, rms (typ) @ 312.5 MHz
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 550 ps
Maximum Output Skew: 25 ps
LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
ESD Protection Exceeds 2 kV (HBM)
Supports 105°C PCB Temperature (Measured with a Thermal Pad)
Available in 6-mm × 6-mm QFN-40 (RHA) Package

产品应用

Wireless Communications
Telecommunications/Networking
Medical Imaging
Test and Measurement Equipment

产品说明

The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1212 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1212 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. The CDCLVP1212 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1212 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1212 is packaged in a small 40-terminal, 6-mm x 6-mm QFN package and is characterized for operation from –40°C to 85°C.

产品器件信息

PART NUMBER	PACKAGE	BODY SIZE (NOM)
CDCLVP1212	QFN (40)	6.00 mm x 6.00 mm

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