CDCLVP215 - 双路 1:5 高速 LVPECL 扇出缓冲器

CDCLVP215是TI德州仪器公司的一款差动产品，CDCLVP215是双路 1:5 高速 LVPECL 扇出缓冲器，本站介绍了CDCLVP215的封装应用图解、特点和优点、功能等，并给出了与CDCLVP215相关的TI元器件型号供参考。

CDCLVP215 - 双路 1:5 高速 LVPECL 扇出缓冲器 - 差动 - 时钟缓冲器 - 德州仪器

产品描述

The CDCLVP215 clock driver distributes two times one differential clock pair of LVPECL, (CLKA, CLKB) to 5 pairs of differential LVPECL clock (QA0..QA4, QB0..QB4) outputs with minimum skew for clock distribution. The CDCLVP215 specifies low output-to-output skew. The CDCLVP215 is specifically designed for driving 50- transmission lines. When an output pair is not used, leaving it open is recommended to reduce power consumption. If only one of the output pairs is used, the other output pair must be identically terminated to 50 .

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLKA or CLKB and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP215 is characterized for operation from –40°C to 85°C.

产品特性

2× One Differential Clock Input Pair LVPECL to 5 Differential LVPECL Clock Outputs
Fully Compatible With LVPECL/LVECL
Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
Open Input Default State
Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
VBB Reference Voltage Output for Single-Ended Clocking
Available in the QFN32 Package
Frequency Range From DC to 3.5 GHz
Pin-to-Pin Compatible With the MC100 Series EP111, LVEP210, ES6111, LVEP111
APPLICATIONS
- Designed for Driving 50- Transmission Lines High Performance Clock Distribution

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