CDCM1802 - 具有可编程除法器和 LVPECL I/O + addl LVCMOS 输出的时钟缓冲器

CDCM1802是TI德州仪器公司的一款分频器产品，CDCM1802是具有可编程除法器和 LVPECL I/O + addl LVCMOS 输出的时钟缓冲器，本站介绍了CDCM1802的封装应用图解、特点和优点、功能等，并给出了与CDCM1802相关的TI元器件型号供参考。

CDCM1802 - 具有可编程除法器和 LVPECL I/O + addl LVCMOS 输出的时钟缓冲器 - 分频器 - 时钟缓冲器 - 德州仪器

产品特性

Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output
Programmable Output Divider for Both LVPECL and LVCMOS Outputs
1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
3.3-V Power Supply (2.5-V Functional)
Signaling Rate Up to 800-MHz LVPECL and 200-MHz LVCMOS
Differential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input Signals
Receiver Input Threshold ±75 mV
16-Pin VQFN Package (3.00 mm × 3.00 mm)

产品应用

Networking and Data Communications
Medical Imaging
Portable Test and Measurement
High-end A/V

产品说明

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.

产品器件信息

PART NUMBER	PACKAGE	BODY SIZE (NOM)
CDCM1802	VQFN (16)	3.00 mm × 3.00 mm

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