CDCM7005-SP - 3.3V 高性能抗辐射 V 类时钟同步器和抖动消除器

CDCM7005-SP是TI德州仪器公司的一款单回路PLL产品，CDCM7005-SP是3.3V 高性能抗辐射 V 类时钟同步器和抖动消除器，本站介绍了CDCM7005-SP的封装应用图解、特点和优点、功能等，并给出了与CDCM7005-SP相关的TI元器件型号供参考。

CDCM7005-SP - 3.3V 高性能抗辐射 V 类时钟同步器和抖动消除器 - 单回路PLL - 时钟抖动消除器 - 德州仪器

产品特性

High Performance LVPECL and LVCMOS PLL Clock Synchronizer
Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection
Accepts LVCMOS Input Frequencies Up to 200 MHz
VCXO_IN Clock is Synchronized to One of the Two Reference Clocks
VCXO_IN Frequencies Up to 2 GHz (LVPECL)
Outputs can be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or Up to 10 LVCMOS Outputs)
Output Frequency is Selectable by x1, /2, /3, /4, /6, /8, /16 on Each Output Individually
Efficient Jitter Cleaning from Low PLL Loop Bandwidth
Low Phase Noise PLL Core
Programmable Phase Offset (PRI_REF and SEC_REF to Outputs)
Wide Charge Pump Current Range From 200 μA to 3 mA
Analog and Digital PLL Lock Indication
Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)
Frequency Hold Over Mode Improves Fail-Safe Operation
Power-Up Control Forces LVPECL Outputs to Tri-State at VCC < 1.5 V
SPI Controllable Device Setting
3.3-V Power Supply
High-Performance 52 Pin Ceramic Quad Flat Pack (HFG)
Rad-Tolerant : 50 kRad (Si) TID
QML-V Qualified, SMD 5962-07230
Military Temperature Range: –55°C to 125°C Tcase
Engineering Evaluation (/EM) Samples are Available (1)

(1) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (for example, no burn-in, and so forth) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life.

产品应用

Low-Jitter Clock Distribution
SERDES Links
Analog Data Converters
Digital-to-Analog Converters

产品说明

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

产品器件信息

PART NUMBER	PACKAGE	BODY SIZE (NOM)
CDCM7005-SP	CFP (52)	13.97 mm × 13.97 mm

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