CDCVF2510A - 具有断电模式的 3.3V 锁相环时钟驱动器

CDCVF2510A是TI德州仪器公司的一款SDR产品，CDCVF2510A是具有断电模式的 3.3V 锁相环时钟驱动器，本站介绍了CDCVF2510A的封装应用图解、特点和优点、功能等，并给出了与CDCVF2510A相关的TI元器件型号供参考。

CDCVF2510A - 具有断电模式的 3.3V 锁相环时钟驱动器 - SDR - 存储器接口时钟和寄存器 - 德州仪器

产品描述

The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510A operates at a 3.3-V VCC and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. The device automically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a low state.

Unlike many products containing PLLs, the CDCVF2510A does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCVF2510A requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCC to ground to use as a simple clock buffer.

The CDCVF2510A is characterized for operation from 0°C to 85°C.

产品特性

Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
Spread Spectrum Clock Compatible
Operating Frequency 20 MHz to 175 MHz
Static Phase Error Distribution at 66 MHz to 166 MHz is ±125 ps
Jitter (cyccyc) at 66 MHz to 166 MHz is |70| ps
Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption vs Current Generation PC133 Devices
Auto Frequency Detection to Disable Device (Power-Down Mode)
Available in Plastic 24-Pin TSSOP
Distributes One Clock Input to One Bank of 10 Outputs
External Feedback (FBIN) Terminal is Used to Synchronize the Outputs to the Clock Input
25- On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
APPLICATIONS
- DRAM Applications
- PLL Based Clock Distributors
- Non-PLL Clock Buffer

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