DAC5674 - 具有 2x/4x 插值滤波器的14 位 400 CommsDAC

DAC5674是TI德州仪器公司的一款高速DAC(>10MSPS)产品，DAC5674是具有 2x/4x 插值滤波器的14 位 400 CommsDAC，本站介绍了DAC5674的封装应用图解、特点和优点、功能等，并给出了与DAC5674相关的TI元器件型号供参考。

DAC5674 - 具有 2x/4x 插值滤波器的14 位 400 CommsDAC - 高速DAC(>10MSPS) - 数模转换器 - 德州仪器

产品描述

The DAC5674 is a 14-bit resolution high-speed digital-to-analog converter (DAC) with integrated 4x-interpolation filter, on-board clock multiplier, and on-chip voltage reference. The device has been designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digital synthesis (DDS) and waveform reconstruction in test and measurement applications.

The 4x-interpolation filter is implemented as a cascade of two 2x-interpolation filters, each of which can be configured for either low-pass or high-pass response. This enables the user to select one of the higher order images present at multiples of the input data rate clock while maintaining a low date input rate. The resulting high IF output frequency allows the user to omit the conventional first mixer in heterodyne transmitter architectures and directly up-convert to RF using only one mixer, thereby reducing system complexity and costs.

In 4x-interpolation low-pass response mode, the DACs excellent spurious free dynamic range (SFDR) at intermediate frequencies located in the first Nyquist zone (up to 40 MHz) allows for multicarrier transmission in cellular base transceiver stations (BTS). The low-pass interpolation mode thereby relaxes image filter requirements by filtering out the images in the adjacent Nyquist zones.

The DAC5674 PLL clock multiplier controls all internal clocks for the digital filters and DAC core. The differential clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock divider of the PLL ensures that the digital filters operate at the correct clock frequencies.

The DAC5674 operates from an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. The digital I/Os are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 500 mW at maximum operating conditions. The DAC5674 provides a nominal full-scale differential current-output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The device has been specifically designed for a differential transformer coupled output with a 50- doubly terminated load. For a 20-mA full-scale output current both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2-dBm output power) are supported. The latter configuration is preferred for optimum performance at high output frequencies and update rates.

An accurate on-chip 1.2-V temperature compensated bandgap reference and control amplifier allows the user to adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage may be applied for maximum flexibility. The device features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby optimizing the power consumption for the system’s need.

The DAC5674 is available in a 48-pin HTQFP Powerpad™ plastic quad flatpack package. The device is characterized for operation over the industrial temperature range of –40°C to 85°C.

产品特性

200-MSPS Maximum Input Data Rate
400-MSPS Maximum Update Rate DAC
76-dBc SFDR Over Full First Nyquist Zone With Single Tone Input Signal (Fout = 21 MHz)
74-dBc ACPR W-CDMA at 15.36 MHz IF
69-dBc ACPR W-CDMA at 30.72 MHz IF
Selectable 2x or 4x Interpolation Filter
- Linear Phase
- 0.05-dB Passband Ripple
- 80-dB Stopband Attenuation
- Stopband Transition 0.4-0.6 Fdata
- Interpolation Filters Configurable in Either Low-Pass or High-Pass Mode, Allows For Selection Higher Order Image
On-chip 2x/4x PLL Clock Multiplier, PLL Bypass Mode
Differential Scalable Current Outputs: 2 mA to 20 mA
On-Chip 1.2-V Reference
1.8-V Digital and 3.3-V Analog Supply Operation
1.8/3.3-V CMOS Compatible Interface
Power Dissipation: 435 mW at 400 MSPS
Package: 48-Pin TQFP
APPLICATIONS
- Cellular Base Transceiver Station Transmit Channel
  - CDMA: W-CDMA, CDMA2000, IS-95
  - TDMA: GSM, IS-136, EDGE/UWC-136
- Test and Measurement: Arbitrary Waveform Generation
- Direct Digital Synthesis (DDS)
- Cable Modem Termination System

Excel is a trademark of Microsoft Corporation. CommsDAC and PowerPAD are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

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