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DS90CR286AT-Q1 - 产品图解:
DS90CR286AT-Q1-3.3V 上升沿数据选通信号 LVDS 接收器 28 位 Channel Link 66MHz
DS90CR286AT-Q1-通道链接I-串行器、解串器-接口
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TI产品 - DS90CR286AT-Q1介绍

DS90CR286AT-Q1 - 3.3V 上升沿数据选通信号 LVDS 接收器 28 位 Channel Link 66MHz

DS90CR286AT-Q1是TI德州仪器公司的一款通道链接I产品,DS90CR286AT-Q1是3.3V 上升沿数据选通信号 LVDS 接收器 28 位 Channel Link 66MHz,本站介绍了DS90CR286AT-Q1的封装应用图解、特点和优点、功能等,并给出了与DS90CR286AT-Q1相关的TI元器件型号供参考。

DS90CR286AT-Q1 - 3.3V 上升沿数据选通信号 LVDS 接收器 28 位 Channel Link 66MHz - 通道链接I - 串行器、解串器 - 德州仪器

产品特性
  • 20 to 66 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Best–in–Class Setup & Hold Times on Rx Outputs
  • Rx Power Consumption < 270 mW (typ) at 66 MHz Worst Case
  • Rx Power-down Mode < 200 μW (max)
  • ESD Rating: 4 kV (HBM), 1 kV (CDM)
  • PLL Requires No External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-Pin DGG (TSSOP) Package
  • Operating Temperature: −40°C to +105°C
  • Automotive AEC-Q100 Grade 2 Qualified
产品应用
  • Video Displays
  • Automotive Infotainment
  • Industrial Printers and Imaging
  • Digital Video Transport
  • Machine Vision
  • OpenLDI-to-RGB Bridge
产品说明

The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. The receiver data outputs strobe on the output clock's rising edge.

The receiver LVDS clock operates at rates from 20 to 66 MHz. The DS90CR286AT-Q1 phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into 28-bit parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps.

The DS90CR286AT-Q1 device is enhanced over prior generation receivers due to a wider data valid time on the receiver output. The DS90CR286AT-Q1 is designed for PCB board chip-to-chip OpenLDI-to-RGB bridge conversion. LVDS data transmission over cable interconnect is not recommended for this device.

Users designing a sub-system with a compatible OpenLDI transmitter and DS90CR286AT-Q1 receiver must ensure an acceptable skew margin budget (RSKM). Details regarding RSKM can be found in the Application Information section.

产品器件信息
PART NUMBERPACKAGEBODY SIZE (NOM)
DS90CR286AT-Q1TSSOP (56)14.00 mm × 6.10 mm
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