• Supports Pixel Clock Frequency up to 170 MHz for WUXGA (1920x1200) and 1080p60 Resolutions with 24-bit Color Depth
• 1-lane or 2-lane FPD-Link III Interface with De-skew Capability
• Single or Dual OpenLDI (LVDS) Transmitter
  • Single Channel: Up to 96 MHz Pixel Clock
  • Dual Channel: Up to 170 MHz Pixel Clock
  • Configurable 18-bit RGB or 24-bit RGB
• Integrated HDCP cipher engine with on-chip key storage
• Supports HDCP Repeater Applications
• High Speed GPIO up to 2.0 Mbps
• Supports up to 15 meters of cable with automatic temperature and aging compensation
• SPI Control Interfaces up to 3.3 Mbps
• I2C (Master/Slave) with 1 Mbps Fast-mode Plus
• Adaptive Receive Equalization
• Image Enhancement (White Balance and Dithering)
• Supports 7.1 Multiple I2S (4 data) Channels
• Backward Compatible to DS90UH925/925AQ-Q1 and DS90UH927Q-Q1 FPD-Link III Serializers
• Automotive Grade Product: AEC-Q100 Grade 2 Qualified

• Automotive Infotainment:
  • Central Information Displays
  • Rear Seat Entertainment Systems
  • Digital Instrument Clusters

The DS90UH948-Q1 is a FPD-Link III Deserializer which, in conjunction with the DS90UH949/947/929-Q1 Serializers, converts 1-lane or 2-lane FPD-Link III streams into a FPD-Link (OpenLDI) interface. The Deserializer is capable of operating over cost-effective 50Ω single-ended coaxial or 100Ω differential shielded twisted-pair (STP) cables. It recovers the data from one or two FPD-Link III serial streams and translates it into dual pixel FPD-Link (8 LVDS data lanes + clock) supporting video resolutions up to WUXGA and 1080p60 with 24-bit color depth. This provides a bridge between HDMI enabled sources such as GPUs to connect to existing LVDS displays or Application Processors.

The FPD-Link III interface supports video and audio data transmission and full duplex control, including I2C and SPI communication, over the same differential link. Consolidation of video data and control over two differential pairs reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward compatible mode, the device supports up to WXGA and 720p resolutions with 24-bit color depth over a single differential link.

The device automatically detects the FPD-Link III channels and provides a clock alignment and de-skew functionality without the need for any special training patterns. This ensures skew phase tolerance from mismatches in interconnect wires such as PCB trace routing, cable pair-to-pair length differences, and connector imbalances.