DS92LX1621 - 10 - 50 MHz DC 平衡频道链接 III 双向性控制串行器

DS92LX1621是TI德州仪器公司的一款频道链接III产品，DS92LX1621是10 - 50 MHz DC 平衡频道链接 III 双向性控制串行器，本站介绍了DS92LX1621的封装应用图解、特点和优点、功能等，并给出了与DS92LX1621相关的TI元器件型号供参考。

DS92LX1621 - 10 - 50 MHz DC 平衡频道链接 III 双向性控制串行器 - 频道链接III - 串行器、解串器 - 德州仪器

产品描述

The DS92LX1621 / DS92LX1622 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex back channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bi-directional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) or parity bit to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The sleep function provides a power-savings mode and a remote wake up interrupt for signaling of a remote device.

The Serializer is offered in a 32-pin WQFN package, and Deserializer is offered in a 40-pin WQFN package.

产品特性

Configurable Data Throughput
- 12–bit (min) up to 600 Mbits/sec
- 16–bit (def) up to 800 Mbits/sec
- 18–bit (max) up to 900 Mbits/sec
10 MHz to 50 MHz Input Clock Support
Embedded Clock with DC Balanced Coding to Support AC-Coupled Interconnects
Capable to Drive up to 10 Meters Shielded Twisted-Pair
Bi-Directional Control Interface Channel with I2C Support
I2C Interface for Device Configuration. Single-pin ID Addressing
16–bit Data Payload with CRC (Cyclic Redundancy Check) for Checking Data Integrity with Programmable Data Transmission Error Detection and Interrupt Control
Up to 6 Programmable GPIO’s
AT-SPEED BIST Diagnosis Feature to Validate Link Integrity
Individual Power-Down Controls for Both SER and DES
User-Selectable Clock Edge for Parallel Data on Both SER and DES
Integrated Termination Resistors
1.8V- or 3.3V-Compatible Parallel Bus Interface
Single Power Supply at 1.8V
IEC 61000–4–2 ESD Compliant
No Reference Clock Required on Deserializer
Programmable Receive Equalization
LOCK Output Reporting Pin to Ensure Link Status
EMI/EMC Mitigation
- DES Programmable Spread Spectrum (SSCG) Outputs
- DES Receiver Staggered Outputs
Temperature Range −40°C to +85°C
SER Package: 32 Pin WQFN (5mm × 5mm)
DES Package: 40 Pin WQFN (6mm × 6mm)

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