LMK04010 - 具有级联 PLL 的低噪声时钟抖动清洁器

LMK04010是TI德州仪器公司的一款无产品，LMK04010是具有级联 PLL 的低噪声时钟抖动清洁器，本站介绍了LMK04010的封装应用图解、特点和优点、功能等，并给出了与LMK04010相关的TI元器件型号供参考。

LMK04010 - 具有级联 PLL 的低噪声时钟抖动清洁器 - 无 -

LMK04010 (正在供货)

具有级联PLL的低噪声时钟抖动清洁器 $("#ab_prod - 德州仪器

产品描述

The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.

The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1.

The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.

产品特性

Cascaded PLLatinum PLL Architecture

PLL1

Phase detector rate of up to 40 MHz

Integrated Low-Noise Crystal Oscillator Circuit

Dual redundant input reference clock with LOS

PLL2

Normalized [1 Hz] PLL noise floor of -224 dBc/Hz

Phase detector rate up to 100 MHz

Input frequency-doubler

Integrated Low-Noise VCO

Ultra-Low RMS Jitter Performance

150 fs RMS jitter (12 kHz – 20 MHz)

200 fs RMS jitter (100 Hz – 20 MHz)

LVPECL/2VPECL, LVDS, and LVCMOS outputs

Support clock rates up to 1080 MHz

Default Clock Output (CLKout2) at power up

Five dedicated channel divider and delay blocks

Pin compatible family of clocking devices

Industrial Temperature Range: -40 to 85 °C

3.15 V to 3.45 V operation

Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

Target Applications

Data Converter Clocking

Wireless Infrastructure

Networking, SONET/SDH, DSLAM

Medical

Military / Aerospace

Test and Measurement

Video

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