LMK61PD0A2 - 引脚模式，差分，OE 高电平，25ppm

LMK61PD0A2是TI德州仪器公司的一款无产品，LMK61PD0A2是引脚模式，差分，OE 高电平，25ppm，本站介绍了LMK61PD0A2的封装应用图解、特点和优点、功能等，并给出了与LMK61PD0A2相关的TI元器件型号供参考。

LMK61PD0A2 - 引脚模式，差分，OE 高电平，25ppm - 无 - 振荡器 - 德州仪器

产品特性

Ultra-low Noise, High Performance
- Jitter: 90 fs RMS typical fOUT > 100 MHz
- PSRR: -70 dBc, robust supply noise immunity
Flexible Output Frequency and Format; User Selectable
- Frequencies: 62.5 MHz, 100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 312.5 MHz
- Formats: LVPECL, LVDS or HCSL
Total frequency tolerance of ± 50 ppm
Internal memory stores multiple start-up configurations, selectable through pin control
3.3V operating voltage
Industrial temperature range (-40ºC to +85ºC)
7 mm x 5 mm 8-pin package

产品应用

High-performance replacement for crystal-, SAW-, or silicon-based Oscillators
Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN
Test and Measurement
Medical Imaging
FPGA, Processor Attach

产品说明

The LMK61PD0A2 is an ultra-low jitter PLLatinumTM pin selectable oscillator that generates commonly used reference clocks. The device is pre-programmed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.

产品器件信息

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LMK61PD0A2	8-pin QFM (SIA)	7.0 mm x 5.0 mm

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