The Texas Instruments PCI2060 is a 32-bit, asynchronous, PCI-to-PCI bridge that is fully compliant with the PCI Local Bus Specification, Revision 2.3 and the PCI-to-PCI Bridge Specification, Revision 1.1. The PCI2060 bridge makes it possible for the primary and secondary bus clocks to be completely asynchronous and supports the PCI clock frequency up to 66 MHz.

The PCI2060 bridge is architecture-configurable for the PCI Bus Power Interface Specification. It can be configured to support either revision 1.0 or revision 1.1. Power conservation is made possible by using 1.8-V core logic with a universal PCI interface compatible with 3.3-V and 5-V PCI signaling environments.

The PCI2060 bridge allows the primary and secondary buses to operate concurrently. It provides independent read and write buffers for each direction and utilizes pipeline architecture for burst data transfer.

The PCI2060 bridge makes it possible to overcome the electrical loading limit of ten devices per PCI bus and one PCI device per expansion slot by creating hierarchical buses. Each PCI2060 bridge that is added to the system creates a new PCI bus. The PCI2060 bridge provides a two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external arbiter.

The PCI2060 bridge provides CompactPCI hot-swap support that is compliant with the PICMG CompactPCI Hot-Swap Specification, Revision 1.0.

• Fully Supports PCI Local Bus Specification, Revision 2.3
• Fully Supports PCI-to-PCI Bridge Specification, Revision 1.1
• Fully Supports Advanced Configuration Power Interface (ACPI) Specification
• Architecture Configurable for PCI Bus Power Management Interface Specification, Revision 1.0 and Revision 1.1
• Two 32-Bit, 66-MHz Asynchronous PCI Buses
• 1.8-V Core Logic with Universal PCI Interface Compatible with 3.3-V and 5-V PCI Signaling Environments
• Provides Concurrent Primary and Secondary Bus Operations
• Independent Read and Write Buffers for Each Direction
• Burst Data Transfers With Pipeline Architecture To Maximize Data Throughput In Both Directions
• Up To Three Delayed Transactions For All PCI Configuration, I/O, and Memory Read Commands In Both Directions
• Provides 10 Secondary PCI Bus Clock Outputs
• Provides Internal Two-Tier Arbitration For Up To Nine Secondary Bus Masters
• Provides External Arbitration Option
• Provides CompactPCI™ Hot-Swap Functionality
• Provides a 4-Terminal General-Purpose I/O Interface
• Provides an IEEE Standard 1149.1 Joint Test Action Group (JTAG) Interface
• Packaged in 256-Terminal PBGA Package

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