SCAN921226H是TI公司的一款BLVDS/LVDS串行器/解串器(<100MHz)产品，SCAN921226H是具有 IEEE 1149.1 测试访问的高温 20MHz - 80MHz 10 位解串器，本页介绍了SCAN921226H的产品说明、应用、特性等，并给出了与SCAN921226H相关的TI元器件型号供参考。
SCAN921226H - 具有 IEEE 1149.1 测试访问的高温 20MHz - 80MHz 10 位解串器 - BLVDS/LVDS串行器/解串器(<100MHz) - 串行器、解串器 - TI公司（Texas Instruments，德州仪器）
The SCAN921025H transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The SCAN921226H receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock.
Both devices are compliant with IEEE 1149.1 Standard for Boundary Scan Test. IEEE 1149.1 features provide the design or test engineer access via a standard Test Access Port (TAP) to the backplane or cable interconnects and the ability to verify differential signal integrity. The pair of devices also features an at-speed BIST mode which allows the interconnects between the Serializer and Deserializer to be verified at-speed.
The SCAN921025H transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock ensures a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the SCAN921025H output pins into tri-state to achieve a high impedance state. The PLL can lock to frequencies between 20 MHz and 80 MHz.
- High Temperature Operation to 125°C
- IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode
- Clock Recovery from PLL Lock to Random Data Patterns
- Ensured Transition Every Data Transfer Cycle
- Chipset (Tx + Rx) Power Consumption < 600 mW (Typ) @ 80 MHz
- Single Differential Pair Eliminates Multi-Channel Skew
- 800 Mbps Serial Bus LVDS Data Rate (at 80 MHz Clock)
- 10-bit Parallel Interface for 1 Byte Data Plus 2 Control Bits
- Synchronization Mode and LOCK Indicator
- Programmable Edge Trigger on Clock
- High Impedance on Receiver Inputs When Power is Off
- Bus LVDS Serial Output Rated for 27? Load
- Small 49-Lead NFBGA Package
