The SMJ320C6203 device is part of the SMJ320C62x™ fixed-point DSP generation in the SMJ320C6000™ DSP platform. The C62x™ DSP devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

The SMJ320C62x™DSP offers cost-effective solutions to high-performance DSP-programming challenges. The SMJ320C6203 has a performance capability of up to 1600 MIPS at a clock rate of 200 MHz. The C6203 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6203 can produce two multiply-accumulates (MACs) per cycle for a total of 400 million MACs per second (MMACS). The C6203 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6203 device program memory consists of two blocks, with a 256K-byte block configured as memory-mapped program space, and the other 128K-byte block user-configurable as cache or memory-mapped program space. Data memory for the C6203 consists of two 256K-byte blocks of RAM.

The C6203 device has a powerful and diverse set of peripherals. The peripheral set includes three multichannel buffered serial ports (McBSPs), two general-purpose timers, a 32-bit expansion bus that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C62x™ devices have a complete set of development tools that includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

• High-Performance Fixed-Point Digital Signal Processor (DSP) – SMJ320C62x™
  • 5-ns Instruction Cycle Time
  • 200-MHz Clock Rate
  • Eight 32-Bit Instructions/Cycle
  • 1600 Million Instructions Per Second (MIPS)
• 429-Pin Ball Grid Array (BGA) Package (GLP Suffix)
• VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) C62x™ DSP Core
  • Eight Highly Independent Functional Units:
    • Six Arithmetic Logic Units (ALUs) (32-/40-Bit)
    • Two 16-Bit Multipliers (32-Bit Result)
  • Load-Store Architecture With 32 32-Bit General-Purpose Registers
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
• Instruction Set Features
  • Byte-Addressable (8-, 16-, 32-Bit Data)
  • 8-Bit Overflow Protection
  • Saturation
  • Bit-Field Extract, Set, Clear
  • Bit-Counting
  • Normalization
• 7M-Bit On-Chip SRAM
  • 3M-Bit Internal Program/Cache (96K 32-Bit Instructions)
  • 4M-Bit Dual-Access Internal Data (512K Bytes)
    • Organized as Two 256K-Byte Blocks for Improved Concurrency
• Flexible Phase-Locked-Loop (PLL) Clock Generator
• 32-Bit External Memory Interface (EMIF)
  • Glueless Interface to Synchronous Memories: SDRAM or SBSRAM
  • Glueless Interface to Asynchronous Memories: SRAM and EPROM
  • 52M-Byte Addressable External Memory Space
• Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
• 32-Bit Expansion Bus
  • Glueless/Low-Glue Interface to Popular PCI Bridge Chips
  • Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses
  • Master/Slave Functionality
  • Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals
• Three Multichannel Buffered Serial Ports (McBSPs)
  • Direct Interface to T1/E1, MVIP, SCSA Framers
  • ST-Bus-Switching Compatible
  • Up to 256 Channels Each
  • AC97-Compatible
  • Serial-Peripheral Interface (SPI) Compatible (Motorola™)
• Two 32-Bit General-Purpose Timers
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• 0.15-um/5-Level Metal Process
  • CMOS Technology
• 3.3-V I/Os, 1.5-V Internal

SMJ320C62x, VelociTI, and C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. SMJ320C6000 and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation.