SN54ABT8543 - 具有八路寄存总线收发器的扫描测试设备

SN54ABT8543是TI德州仪器公司的一款边界扫描(JTAG)逻辑产品，SN54ABT8543是具有八路寄存总线收发器的扫描测试设备，本站介绍了SN54ABT8543的封装应用图解、特点和优点、功能等，并给出了与SN54ABT8543相关的TI元器件型号供参考。

SN54ABT8543 - 具有八路寄存总线收发器的扫描测试设备 - 边界扫描(JTAG)逻辑 - 特殊逻辑 - 德州仪器

产品描述

The 'ABT8543 scan test devices with octal registered bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F543 and 'ABT543 octal registered bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal registered bus transceivers.

Data flow in each direction is controlled by latch-enable ( and ), chip-enable ( and ), and output-enable ( and ) inputs. For A-to-B data flow, the device operates in the transparent mode when and are both low. When either or is high, the A data is latched. The B outputs are active when and are both low. When either or is high, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B, but uses , , and .

In the test mode, the normal operation of the SCOPETM registered bus transceiver is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8543 is characterized for operation from -40°C to 85°C.

产品特性

Members of the Texas Instruments SCOPETM Family of Testability Products
Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
Functionally Equivalent to 'F543 and 'ABT543 in the Normal-Function Mode
SCOPETM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
- Parallel-Signature Analysis at Inputs With Masking Option
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Even-Parity Opcodes
Two Boundary-Scan Cells Per I/O for Greater Flexibility
State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DL) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)

SCOPE and EPIC-IIB are trademarks of Texas Instruments Incorporated.

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