SN54ACT16373 - 具有三态输出的 16 位 D 类透明锁存器

SN54ACT16373是TI德州仪器公司的一款D类锁存器产品，SN54ACT16373是具有三态输出的 16 位 D 类透明锁存器，本站介绍了SN54ACT16373的封装应用图解、特点和优点、功能等，并给出了与SN54ACT16373相关的TI元器件型号供参考。

SN54ACT16373 - 具有三态输出的 16 位 D 类透明锁存器 - D类锁存器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

The SN54ACT16373 and 74ACT16373 are 16-bit D-type transparent latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data (D) inputs if enable C is taken high. When C is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components.

does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The 74ACT16373 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN54ACT16373 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16373 is characterized for operation from -40°C to 85°C.

产品特性

Members of the Texas Instruments WidebusTM Family
Inputs Are TTL-Voltage Compatible
3-State Bus Driving True Outputs
Full Parallel Access for Loading
Flow-Through Architecture Optimizes PCB Layout
Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Shrink Small-Outline (DL) 300-mil Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

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