The SN74ALS568A decade counter and ´ALS569A binary counters are programmable, count up or down, and offer both synchronous and asynchronous clearing. All synchronous functions are executed on the positive-going edge of the clock (CLK) input.

The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). Asynchronous (direct) clearing overrides all other functions of the device, while synchronous clearing overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by holding load () low during a positive-going clock transition. The counting function is enabled only when enable P (ENP\) and enable T (ENT\) are low and ACLR\, SCLR\, and are high. The up/down (U/D\) input controls the direction of the count. These counters count up when U/D\ is high and count down when U/D\ is low.

A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of . ENT\ is fed forward to enable the ripple-carry output (RCO\) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum (9 or 15) when counting up. The clocked carry output (CCO\) produces a low-level pulse for a duration equal to that of the low level of the clock when is low and the counter is enabled (both ENP\ and ENT\ are low); otherwise, CCO\ is high. CCO\ does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting or CCO\ of the first counter to ENT\ of the next counter. However, for very high-speed counting, should be used for cascading since CCO\ does not become active until the clock returns to the low level.

The SN54ALS569A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.

• 3-State Q Outputs Drive Bus Lines Directly
• Counter Operation Independent of 3-State Output
• Fully Synchronous Clear, Count, and Load
• Asynchronous Clear Is Also Provided
• Fully Cascadable
• Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

• SN74LVC32A - 四路 2 输入正或门
• TMS320C6720 - TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point DSPs
• SN74LV138AT - 3 线路到 8 线路解码器/多路解复用器
• TPS3824-33 - 具有看门狗输入、复位、/复位的电源电压监控器
• SN54AS1000A - 四路 2 输入正与非缓冲器/驱动器
• TLC5930 - 12 通道 LED 驱动器
• TPS70751-EP - Enhanced Military Plastic Dual-Output Low-Dropout Voltage Regulator with Power Up Sequencing
• TMS320VC5410A - 数字信号处理器
• LM285-2.5 - 微功耗电压参考
• TLV1171 - 1A 固定正电压低压降稳压器