The ’HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

• Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
• Wide Operating Voltage Range of 2 V to 6 V
• Outputs Can Drive Up To 10 LSTTL Loads
• Low Power Consumption, 80-µA Max ICC
• Typical tpd = 15 ns
• ±4-mA Output Drive at 5 V
• Low Input Current of 1 µA Max
• Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception

• SN74ACT573 - 具有三态输出的八路 D 类透明锁存器
• TPS79430 - 超低噪声、高 PSRR、快速射频、高电平启用、250mA 低压降稳压器
• TL16C752C - 具有 64 字节 FIFO 的双路 UART
• MSP430FR5987 - MSP430FR698x(1)、MSP430FR5 98x(1) 混合信号微控制器
• UC1863 - 谐振模式电源控制器
• UCC2818A - BiCMOS 功率因子前置稳压器
• MSP430F6638 - MSP430F6638 混合信号微处理器
• SN74AHCT374 - 具有三态输出的八路 D 类边沿触发器
• CD4504B-EP - 用于 TTL 到 CMOS 或 CMOS 到 CMOS 操作的 CMOS 六路电压电平转换器
• TL16C552 - 具有 16 字节 FIFO 和并行端口的双路 UART