SN54HC138-SP是TI公司的一款解码器/编码器/多路复用器产品，SN54HC138-SP是3 线路至 8 线路解码器/多路解复用器，本页介绍了SN54HC138-SP的产品说明、应用、特性等，并给出了与SN54HC138-SP相关的TI元器件型号供参考。
SN54HC138-SP - 3 线路至 8 线路解码器/多路解复用器 - 解码器/编码器/多路复用器 - 特殊逻辑 - TI公司（Texas Instruments，德州仪器）
The ’HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
- Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
- Wide Operating Voltage Range of 2 V to 6 V
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 80-µA Max ICC
- Typical tpd = 15 ns
- ±4-mA Output Drive at 5 V
- Low Input Current of 1 µA Max
- Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
