SN65LV1224B - 1:10 LVDS 串行器/解串器接收器 100 - 660 Mbps

SN65LV1224B是TI德州仪器公司的一款BLVDS/LVDS串行器/解串器(<100MHz)产品，SN65LV1224B是1:10 LVDS 串行器/解串器接收器 100 - 660 Mbps，本站介绍了SN65LV1224B的封装应用图解、特点和优点、功能等，并给出了与SN65LV1224B相关的TI元器件型号供参考。

SN65LV1224B - 1:10 LVDS 串行器/解串器接收器 100 - 660 Mbps - BLVDS/LVDS串行器/解串器(<100MHz) - 串行器、解串器 - 德州仪器

产品描述

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C.

产品特性

100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 66-MHz System Clock
Pin-Compatible Superset of DS92LV1023/DS92LV1224
Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
Synchronization Mode for Faster Lock
Lock Indicator
No External Components Required for PLL
28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
Industrial Temperature Qualified, TA = −40°C to 85°C
Programmable Edge Trigger on Clock
Flow-Through Pinout for Easy PCB Layout
APPLICATIONS
- Wireless Base Station
- Backplane Interconnect
- DSLAM

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