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SN65LVCP40 - 产品图解:
SN65LVCP40-DC 至 4GBPS 二路 1:2 MUX / 中继器/均衡器
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TI产品 - SN65LVCP40介绍
SN65LVCP40 - DC 至 4GBPS 二路 1:2 MUX / 中继器/均衡器

SN65LVCP40是TI公司的一款复用缓冲器产品,SN65LVCP40是DC 至 4GBPS 二路 1:2 MUX / 中继器/均衡器,本页介绍了SN65LVCP40的产品说明、应用、特性等,并给出了与SN65LVCP40相关的TI元器件型号供参考。

SN65LVCP40 - DC 至 4GBPS 二路 1:2 MUX / 中继器/均衡器 - 复用缓冲器 - 信号调节器 - TI公司(Texas Instruments,德州仪器)

产品描述

The SN65LVCP40 is a signal conditioner and data multiplexer optimized for backplanes. Input equalization and programmable output preemphasis support data rates up to 4 Gbps. Common applications are redundancy switching, signal buffering, or performance improvements on legacy backplane hardware.

The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiplexers (mux). Selectable switch-side loopback supports system testing. System interconnects and serial backplane applications of up to 4 Gbps are supported. Each of the two independent channels consists of a transmitter with a fan-out of two, and a receiver with a 2:1 input multiplexer.

The drivers provide four selectable levels of preemphasis to compensate for transmission line losses. The receivers incorporates receive equalization and compensates for input transmission line loss. This minimizes deterministic jitter in the link. The equalization is optimized to compensate for a FR-4 backplane trace with 5-dB, high-frequency loss between 375 MHz and 1.875 GHz. This corresponds to a 24-inch long FR-4 trace with 6-mil trace width.

This device operates from a single 3.3-V supply. The device has integrated 100- line impedance. The inputs and outputs may be ac coupled for best interconnectivity with other devices such as SERDES I/O or additional XAUI multiplexer buffer. With ac coupling, jitter is the lowest.

The SN65LVCP40 is packaged in a 7 mm × 7 mm × 1 mm QFN (quad flatpack no-lead) lead-free package, and is characterized for operation from -40°C to 85°C.

产品特性

  • Receiver Equalization and Selectable Driver Preemphasis to Counteract High-Frequency Transmission Line Losses
  • Integration of Two-Serial Port
  • Selectable Loopback
  • Typical Power Consumption 650 mW
  • 30-ps Deterministic Jitter
  • On-Chip 100- Receiver and Driver Differential Termination Resistors Eliminate External Components and Reflection from Stubs
  • 3.3-V Nominal Power Supply
  • 48-Terminal QFN (Quad Flatpack) 7mm × 7 mm × 1 mm, 0.5-mm Terminal Pitch
  • Temperature Range: -40°C to 85°C
  • APPLICATIONS
    • Bidirectional Link Replicator
    • Signal Conditioner
    • XAUI 802.3ae Protocol Backplane Redundancy
    • Host Adapter (Applications With Internal and External Connection to SERDES)
    • Signaling Rates DC to 4 Gbps Including XAUI, GbE, FC, HDTV

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