SN74ABT16501是TI公司的一款通用总线收发器(UBT)产品，SN74ABT16501是具有三态输出的 18 位通用总线收发器，本页介绍了SN74ABT16501的产品说明、应用、特性等，并给出了与SN74ABT16501相关的TI元器件型号供参考。
SN74ABT16501 - 具有三态输出的 18 位通用总线收发器 - 通用总线收发器(UBT) - 通用总线功能 - TI公司（Texas Instruments，德州仪器）
These 18-bit universal bus transceivers consist of storage elements that can operate either as D-type latches or D-type flip-flops to allow data flow in transparent or clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and ), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and is active low).
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor and should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing/current-sinking capability of the driver.
The SN54ABT16501 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16501 is characterized for operation from -40°C to 85°C.
- Members of the Texas Instruments WidebusTM Family
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
- Flow-Through Architecture Optimizes PCB Layout
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
Widebus, EPIC-IIB, and UBT are trademarks of Texas Instruments Incorporated.
