SN74ABT16843 - 具有三态输出的 18 位总线接口 D 类锁存器

SN74ABT16843是TI德州仪器公司的一款D类锁存器产品，SN74ABT16843是具有三态输出的 18 位总线接口 D 类锁存器，本站介绍了SN74ABT16843的封装应用图解、特点和优点、功能等，并给出了与SN74ABT16843相关的TI元器件型号供参考。

SN74ABT16843 - 具有三态输出的 18 位总线接口 D 类锁存器 - D类锁存器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

The 'ABT16843 18-bit bus-interface D-type latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The 'ABT16843 can be used as two 9-bit latches or one 18-bit latch. The 18 latches are transparent D-type latches. The device provides true data at its outputs.

A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are in the high-impedance state during power up and power down. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16843 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16843 is characterized for operation from -40°C to 85°C.

产品特性

Members of the Texas Instruments WidebusTM Family
State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
High-Impedance State During Power Up and Power Down
High-Drive Outputs (-32-mA IOH, 64-mA IOL)
Package Options Include Plastic Thin Shrink Small-Outline (DGG), 300-mil Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.

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