The 'ABTH32318 consist of three 18-bit registered input/output (I/O) ports. These registers combine D-type latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations of real-time and stored data can be exchanged among the three ports.

Data flow in each direction is controlled by the output-enable (OEA\, OEB\, and OEC\), select-control (SELA, SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock (CLKA, CLKB, and CLKC) inputs. The A data register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLKA is held at a high or low logic level. If LEA is low, data is stored on the low-to-high transition of CLKA. Output data selection is accomplished by the select-control pins. All three ports have active-low output enables, so when the output-enable input is low, the outputs are active; when the output-enable input is high, the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ABTH32318 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH32318 is characterized for operation from -40°C to 85°C.

• Members of the Texas Instruments Widebus+TM Family
• State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
• UBETM (Universal Bus Exchanger) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
• High-Impedance State During Power Up and Power Down
• Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
• High-Drive Outputs (-32-mA IOH, 64-mA IOL)
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include 80-Pin Plastic Thin Quad Flat (PN) Package With 12 × 12-mm Body Using 0.5-mm Lead Pitch and 84-Pin Ceramic Quad Flat (HT) Package

  Widebus+, EPIC-IIB, and UBE are trademarks of Texas Instruments Incorporated.