SN74ALVCH162260是TI公司的一款D类锁存器产品，SN74ALVCH162260是具有三态输出的 12 位至 24 位多路复用 D 类锁存器，本页介绍了SN74ALVCH162260的产品说明、应用、特性等，并给出了与SN74ALVCH162260相关的TI元器件型号供参考。
SN74ALVCH162260 - 具有三态输出的 12 位至 24 位多路复用 D 类锁存器 - D类锁存器 - 触发器/锁存器/寄存器 - TI公司（Texas Instruments，德州仪器）
This 12-bit to 24-bit multiplexed D-type latch is designed for 1.65-V to 3.6-VCC operation.
The SN74ALVCH162260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory-interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B\, OE2B\, and OEA\) inputs control the bus transceiver functions. The OE1B\ and OE2B\ control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162260 is characterized for operation from –40°C to 85°C.
- Member of the Texas Instruments Widebus™ Family
- EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
- B-Port Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Package Options Include Thin-Shrink Small-Outline (DGG) and Plastic Shrink Small-Outline (DL) Packages
NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
