SN74AUC16374 - 具有三态输出的 16 位边沿 D 类触发器

SN74AUC16374是TI德州仪器公司的一款D类触发器产品，SN74AUC16374是具有三态输出的 16 位边沿 D 类触发器，本站介绍了SN74AUC16374的封装应用图解、特点和优点、功能等，并给出了与SN74AUC16374相关的TI元器件型号供参考。

SN74AUC16374 - 具有三态输出的 16 位边沿 D 类触发器 - D类触发器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

产品特性

Member of the Texas Instruments Widebus™ Family
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
Ioff Supports Partial-Power-Down Mode Operation
Sub-1-V Operable
Max tpd of 2.8 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

DESCRIPTION/ORDERING INFORMATION

This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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