The SN74CBTU4411 is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low ON-state resistance (ron). The device utilizes an internal charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ron. The low and flat ron allows for minimal propagation delay and supports rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Matched ron and I/O capacitance among channels results in extremely low differential and rising/falling edge skew. This allows the device to show optimal performance in DDR-II applications.

The device is organized as an 11-bit 1-of-4 multiplexer/demultiplexer with a single switch-enable (EN)\ input. When EN\ is low, the switch is enabled and the H port is connected to one of the D ports. Ports D0 to D9 for the disabled channels are connected to VBIAS through a 400 resistor. DQS_EN determines the output voltage for the disabled D10 ports. When DQS_EN is low, this voltage is VBIAS. When DQS_EN is high, the disabled D10 ports are connected to an internal voltage (VBIAS_DQS) source, which is approximately equal to 0.7 VDD.

When EN\ is high, all the channels are disabled. Ports D0 to D9 are connected to VBIAS. For the D10 port, the disabled output voltage is determined by the DQS_EN input. When DQS_EN is low, this voltage is VBIAS. When DQS_EN is high, this voltage is VDD.

The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. The EN\ and TC inputs determine the internal termination for S0 and S1 inputs. When EN\ is low, the termination is determined by the TC input. When both EN\ and TC are low, termination resistors are disconnected from the S inputs. When EN\ is low and TC is high, both pullup and pulldown resistors are connected to the S inputs. When EN\ is high, only the pulldown termination resistors are connected to the S inputs, regardless of the voltage level at the TC input.

• Supports SSTL_18 Signaling Levels
• Suitable for DDR-II Applications
• D-Port Outputs Are Precharged by Bias Voltage (VBIAS)
• Internal Termination for Control Inputs
• High Bandwidth (334 MHz Min)
• Low and Flat ON-State Resistance (ron) Characteristics, (ron = 17 Max)
• Internal 400- Pulldown Resistors
• Low Differential and Rising/Falling Edge Skew
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22
  • 2000-V Human-Body Model (A114-B, Class II)
  • 1000-V Charged-Device Model (C101)