SN74LV8154 - 具有三态输出寄存器的双路 16 位二进制计数器

SN74LV8154是TI德州仪器公司的一款计数器/算术/奇偶校验功能产品，SN74LV8154是具有三态输出寄存器的双路 16 位二进制计数器，本站介绍了SN74LV8154的封装应用图解、特点和优点、功能等，并给出了与SN74LV8154相关的TI元器件型号供参考。

SN74LV8154 - 具有三态输出寄存器的双路 16 位二进制计数器 - 计数器/算术/奇偶校验功能 - 特殊逻辑 - 德州仪器

产品特性

Can Be Used as Two 16-Bit Counters or a Single 32-Bit Counter
8 bit counter read bus
2-V to 5.5-V VCC Operation
Maximum tpd of 25 ns at 5 V (RCLK to Y)
Typical VOLP (Output Ground Bounce) < 0.7 V at VCC = 5 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) > 4.4 V at VCC = 5 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

产品应用

Up Counters
Dual Up Counters

产品说明

The SN74LV8154 device is a dual 16-bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.

The counters have dedicated clock inputs. The counters share a clocked storage register to sample and save the counter contents. Both counters share an asynchronous clear input. The 32-bit storage register can be mapped on the output bus 8-bits at a time. Four bus reads are needed to access the contents of both stored counts. The two counters can be chained by connecting CLKBEN to RCOA. All clocks are positive edge triggered. All other inputs are active low.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

产品器件信息

PART NUMBER	PACKAGE	BODY SIZE (NOM)
SN74LV8154N	PDIP (20)	6.50 mm x 4.40 mm
SN74LV8154PW	TSSOP (20)	26.92 mm x 6.35 mm

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