SN74LVC16373A-EP - 具有三态输出的增强型产品 16 位 D 类透明锁存器

SN74LVC16373A-EP是TI德州仪器公司的一款D类锁存器产品，SN74LVC16373A-EP是具有三态输出的增强型产品 16 位 D 类透明锁存器，本站介绍了SN74LVC16373A-EP的封装应用图解、特点和优点、功能等，并给出了与SN74LVC16373A-EP相关的TI元器件型号供参考。

SN74LVC16373A-EP - 具有三态输出的增强型产品 16 位 D 类透明锁存器 - D类锁存器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

产品特性

Member of the Texas Instruments Widebus™ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.2 ns at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode Operation
Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

DESCRIPTION/ORDERING INFORMATION

This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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