• Controlled Baseline
  • One Assembly Site
  • One Test Site
  • One Fabrication Site
• Extended Temperature Performance of -55°C to 125°C
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product Change Notification
• Qualification Pedigree(1)
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 5.9 ns at 3.3 V
• Low Power Consumption, 10 µA Max ICC
• ±24 mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

DESCRIPTION/ORDERING INFORMATION

This dual 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G02 performs the Boolean function Y = A + B or Y = A•B in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.