SN74LVC2G74-EP - 具有清零和预设功能的增强型产品单路上升沿 D 类触发器

SN74LVC2G74-EP是TI德州仪器公司的一款无产品，SN74LVC2G74-EP是具有清零和预设功能的增强型产品单路上升沿 D 类触发器，本站介绍了SN74LVC2G74-EP的封装应用图解、特点和优点、功能等，并给出了与SN74LVC2G74-EP相关的TI元器件型号供参考。

SN74LVC2G74-EP - 具有清零和预设功能的增强型产品单路上升沿 D 类触发器 - 无 - 小尺寸逻辑器件 - 德州仪器

产品描述

产品特性

Controlled Baseline
- One Assembly Site
- One Test Site
- One Fabrication Site
Extended Temperature Performance of –55°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree(1)
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 7.9 ns at 3.3 V
Low Power Consumption, 10 µA Max ICC
±24 mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial Power Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

DESCRIPTION/ORDERING INFORMATION

This single positive edge triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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