SN74LVC373A-EP - 具有三态输出的增强型产品八路 D 类透明锁存器

SN74LVC373A-EP是TI德州仪器公司的一款D类锁存器产品，SN74LVC373A-EP是具有三态输出的增强型产品八路 D 类透明锁存器，本站介绍了SN74LVC373A-EP的封装应用图解、特点和优点、功能等，并给出了与SN74LVC373A-EP相关的TI元器件型号供参考。

SN74LVC373A-EP - 具有三态输出的增强型产品八路 D 类透明锁存器 - D类锁存器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

产品特性

Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Extended Temperature Performance of -55°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree(1)
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 7.5 ns at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
Ioff Supports Partial-Power-Down Mode Operation

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

DESCRIPTION/ORDERING INFORMATION

The SN74LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74LVC373A is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

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