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SN74LVC573A-Q1 - 产品图解:
SN74LVC573A-Q1-汽车类具有三态输出的八路透明 D 类锁存器
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TI产品 - SN74LVC573A-Q1介绍
SN74LVC573A-Q1 - 汽车类具有三态输出的八路透明 D 类锁存器

SN74LVC573A-Q1是TI公司的一款D类锁存器产品,SN74LVC573A-Q1是汽车类具有三态输出的八路透明 D 类锁存器,本页介绍了SN74LVC573A-Q1的产品说明、应用、特性等,并给出了与SN74LVC573A-Q1相关的TI元器件型号供参考。

SN74LVC573A-Q1 - 汽车类具有三态输出的八路透明 D 类锁存器 - D类锁存器 - 触发器/锁存器/寄存器 - TI公司(Texas Instruments,德州仪器)

产品描述
产品特性

  • Qualified for Automotive Applications
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Operates From 2 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 6.9 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)> 2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Partial-Power-Down Mode Operation

DESCRIPTION/ORDERING INFORMATION

The SN74LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

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