These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible.

The 'LS138, SN54S138, and SN74S138A decode one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

All of these decoder/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design.

The SN54LS138 and SN54S138 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS138 and SN74S138A are characterized for operation from 0°C to 70°C.

• Designed Specifically for High-Speed:
  • Memory Decoders
  • Data Transmission Systems
• 3 Enable Inputs to Simplify Cascading and/or Data Reception
• Schottky-Clamped for High Performance

• TLVH432A - 低电压可调节精度并联稳压器
• SN74CBTD16211 - 具有电平转换功能的 24 位 FET 总线开关
• UC1854 - 高功率因子前置稳压器
• TLC1542 - 10 位，38kSPS ADC 串行输出，片上系统时钟，11 通道
• CY74FCT16501T - 具有三态输出的 18 位通用总线收发器
• DS10CP154A - 1.5 Gbps 4x4 LVDS 交叉点交换器
• SE556 - 双精度定时器
• SN54HC175 - 具有清零功能的四路 D 类触发器
• UCC2813-1-Q1 - 汽车类低功率 BiCMOS 电流模式 PWM
• UCC1805 - 低功耗 BiCMOS 电流模式 PWM